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| MC10159 Quad 2-Input Multiplexer (Inverting) The MC10159 is a quad two channel multiplexer with enable. It incorporates common enable and common data select inputs. The select input determines which data inputs are enabled. A high (H) level enables data inputs D00, D10, D20, and D30. A low (L) level enables data inputs D01, D11, D21, and D31. Any change on the data inputs will be reflected at the outputs while the enable is low. Input levels are inverted at the output. * PD=218 mW typ/pkg (No Load) * tpd=2.5 ns typ (Data to Q) * 3.2 ns typ (Select to Q) * tr, tf=2.5 ns typ (20%-80%) LOGIC DIAGRAM SELECT 9 D01 5 D00 6 D11 3 D10 4 ENABLE 7 D21 12 D20 13 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week PLCC-20 FN SUFFIX CASE 775 VCC = PIN 16 VEE = PIN 8 1 Q0 PDIP-16 P SUFFIX CASE 648 1 1 10159 AWLYYWW http://onsemi.com MARKING DIAGRAMS 16 CDIP-16 L SUFFIX CASE 620 1 16 MC10159P AWLYYWW MC10159L AWLYYWW 2 Q1 15 Q2 D31 10 D30 11 14 Q3 TRUTH TABLE Enable L L L L H Select L L H H X D0 X X L H X D1 L H X X X Q H L H L L DIP PIN ASSIGNMENT Q0 Q1 D11 D10 D01 D00 ENABLE VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q2 Q3 D20 D21 D30 D31 SELECT ORDERING INFORMATION Device MC10159L MC10159P MC10159FN Package CDIP-16 PDIP-16 PLCC-20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). (c) Semiconductor Components Industries, LLC, 2002 1 January, 2002 - Rev. 7 Publication Order Number: MC10159/D MC10159 ELECTRICAL CHARACTERISTICS Test Limits Pin Under Test 8 9 5 5 1 1 1 1 0.5 -1.060 -1.890 -1.080 -1.655 -0.890 -1.675 -30C Min Max 58 360 400 0.5 -0.960 -1.850 -0.980 -1.630 -0.810 -1.650 Min +25C Typ 42 Max 53 225 250 0.3 -0.890 -1.825 -0.910 -1.595 -0.700 -1.615 Min +85C Max 58 225 250 Unit mAdc Adc Adc Vdc Vdc Vdc Vdc ns t5+1- t9+1- t7+1- t1+ t1- 1 1 1 1 1 1.1 1.5 1.4 1.0 1.0 3.8 5.3 5.3 3.7 3.7 1.2 1.5 1.5 1.1 1.1 2.5 3.2 2.5 2.5 2.5 3.3 5.0 5.0 3.5 3.5 1.1 1.5 1.4 1.0 1.0 3.8 5.3 5.3 3.7 3.7 Characteristic Power Supply Drain Current Input Current Symbol IE IinH IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Logic 1 Logic 0 Logic 1 Logic 0 VOH VOL VOHA VOLA Switching Times (50 Load) Propagation Delay Rise Time Fall Time Data Input Select Input Enable Input (20 to 80%) (20 to 80%) ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) @ Test Temperature -30C +25C +85C Pin Under Test 8 9 5 5 1 1 1 1 5 9 9 +1.11V t5+1- t9+1- t7+1- t1+ t1- 1 1 1 1 1 6 3, 12 9 9 +0.31V 6 Pulse In 5 9 7 5 5 Pulse Out 1 1 1 1 1 6 9 5 5 VIHmax -0.890 -0.810 -0.700 VILmin -1.890 -1.850 -1.825 VIHAmin -1.205 -1.105 -1.035 VILAmax -1.500 -1.475 -1.440 VEE -5.2 -5.2 -5.2 (VCC) Gnd 16 16 16 16 16 16 16 16 +2.0 V 16 16 16 16 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE 8 8 8 8 8 8 8 8 -3.2 V 8 8 8 8 Characteristic Power Supply Drain Current Input Current Symbol IE IinH IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Propagation Delay Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) Data Input Select Input Enable Input (20 to 80%) (20 to 80%) VOH VOL VOHA VOLA Rise Time Fall Time Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. http://onsemi.com 2 MC10159 PACKAGE DIMENSIONS PLCC-20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C B -N- Y BRK D -L- -M- W D X V A Z R 0.007 (0.180) 0.007 (0.180) M 0.007 (0.180) U M T L-M M S N S S 0.007 (0.180) T L-M N S Z 20 1 G1 0.010 (0.250) S T L-M S N S VIEW D-D T L-M T L-M S N N S H 0.007 (0.180) M T L-M S N S M S S K1 K C E 0.004 (0.100) G G1 0.010 (0.250) S T L-M J -T- SEATING PLANE F VIEW S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). 0.007 (0.180) M T L-M S N S VIEW S S N S DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2_ 10 _ 0.310 0.330 0.040 --- MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2_ 10 _ 7.88 8.38 1.02 --- http://onsemi.com 3 MC10159 CDIP-16 L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE T -A- 16 9 -B- 1 8 C L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 -T- SEATING PLANE N E F D G 16 PL K M J 16 PL 0.25 (0.010) M M TB S 0.25 (0.010) TA S -A- 16 9 PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R B 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 4 MC10159/D |
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